Specification Analysis of Transactional Memory using ITL and AnaTempura

Transactional memory (TM) is a promising lockfree technique that offers a high-level abstract parallel programming model for future chip multiprocessor (CMP) systems. Moreover it adapts the popular well established paradigm of transaction, thus providing a general and flexible way of allowing programs to atomically read and modify disparate memory locations as a single operation. In this paper, we propose a general and executable specification model for an abstract TM with validation for various correctness conditions of concurrent transactions. This model is constructed within a flexible transition framework that allows the testing of a TM model with animation. Interval Temporal Logic (ITL) and its programming language subset AnaTempura are used to build, execute, and validate this model. To demonstrate this work, we selected a queue example to be executed and illustrated with animation.